The present invention relates to timing analysis in integrated circuit design, and more specifically, to adaptive characterization and instantiation of timing abstracts.
Timing analysis is an important part of integrated circuit (chip) design and helps to ensure that the physical implementation of the chip design meets all timing constraints. The timing analysis may be performed at different levels of accuracy. Generally, for a given circuit, the accuracy, run time, and memory usage associated with timing analysis depend on the complexity of the model used to represent the variables involved in the timing analysis. Models that provide greater accuracy require more memory and longer run times. Thus, improving accuracy is at the cost of higher memory usage and longer run time.